The IEEE 1149.1 JTAG interface was developed to facilitate external access to integrated circuit devices. A JTAG-compatible integrated circuit device typically includes a standardized test access port (TAP) that allows boundary scan operations to be performed by an external TAP controller via the TAP port of the device. All test result outputs may be sent back through the same TAP port.
The standardized JTAG interface originally was used to test printed circuit boards and later found use in testing individual integrated circuits. However, due to their complexity, core-based integrated circuit design has introduced new complexities in that the number of transistors has increased at a greater rate than Input/Output (I/O) pins. Therefore, standard test data register (TDR) cells have been developed that may be grown directly on the integrated circuit. Thus, cell-based TDRs may be placed generally wherever they are needed along the boundary of the integrated circuit's functional circuitry boundary. For the purposes of this disclosure, a cell-based integrated circuit design may be implemented by a circuit designer that lays out an integrated circuit design by connecting together a number of predefined cells. Each cell may include a plurality of transistors that have been integrated together to perform a predefined function. Cells may be maintained in a library, so that a designer may often build a design simply by assembling together cells of transistors rather than laying out each transistor individually.
Conventional designs implement a full Scan Communications bus (SCom) with a unique protocol to handle the debug logic needed for communication. However, the SCom solution, having a similar register addressed structure, has an additional level of clock latency, as well as similar global wiring and area congestion issues.
What is consequently needed is an asynchronous communication mechanism that allows a user to implement their unique internal register-addressed protocol, typically at a chip system speed, and allows data to be asynchronously transferred to and from a JTAG controller at the JTAG interface speed.